Thin-film semiconductor devices formed using non-single-crystal semiconductor films such as polycrystalline and amorphous semiconductor films are used in the display portions and peripheral circuitry of active matrix liquid crystal display devices, image sensors and SRAM devices. "Thin film semiconductor device" refers to a semiconductor film, a thin-film transistor (TFT), or a CMOS type of TFT having a p-channel TFT and an n-channel TFT. "Thin-film semiconductor device" and "TFT" are used interchangeably in this document.
Thin-film semiconductor devices are required to operate at high speeds when used in peripheral circuitry such as a liquid crystal display device. When the operational speed of the thin film semiconductor devices is sufficiently high, switching devices of the display portion and all the peripheral circuitry such as shift registers and analog switches can be integrated onto the liquid crystal substrate using the thin-film semiconductor devices.
If the speed of the thin-film semiconductor devices were to be increased, the range of applications of the thin-film semiconductor devices would be much wider than in the prior art. Prior art applications of the thin-film semiconductor devices are limited to liquid crystal display devices. It has been very difficult to extend the application of the thin-film semiconductor devices to digital and analog circuits where single-crystal MOSFETs are used. This is because the thin-film semiconductor device has a smaller carrier mobility than the carrier mobility of a single-crystal MOSFET. Thus, the speed of the thin-film semiconductor device is slower than the speed of the single crystal MOSFET. However, if the thin-film semiconductor device operates at a speed comparable to that of a single-crystal MOSFET, the thin-film semiconductor devices may be used in digital and analog circuits where only single-crystal MOSFETs are used in the prior art.
The thin-film semiconductor device differs from a single-crystal MOSFET in that it is formed on an insulating substance. This means that it is not affected by the problems experienced by the single-crystal MOSFET. Problems such as noise transmitted through the substrate and latch-up caused by current flowing through the substrate are examples. Therefore, increasing the speed of a thin-film semiconductor device is a technical objective.
In order to increase the speed of the thin-film semiconductor device, the following problems described must be solved. An example of a thin-film semiconductor device is shown in FIG. 56A and an equivalent circuit diagram of this thin-film semiconductor device is shown in FIG. 56B. In FIG. 56B, Rc1 and Rc2 are contact resistances of a contact portion 412 between wiring 408 and a source portion 404 and a contact portion 414 between wiring 410 and a drain portion 406. Rs is the source resistance of the source portion 404, Rch is the channel resistance of a channel portion 402, and Rd is the drain resistance of the drain portion 406.
In order to increase the speed of this thin-film semiconductor device, it is first necessary to reduce the total value of the serially connected resistances Rc1, Rs, Rch, Rd, and Rc2 when the transistor is ON. If the total resistance when the transistor is ON is denoted by Ron, Ron is the sum of the on-state channel resistance Rch(on) and the overall parasitic resistance Rp of the rest of the components. In other words:
Page 02 ##EQU1##
Therefore, in order to achieve a faster thin-film semiconductor device, both the on-state channel resistance Rch(on) and the overall parasitic resistance Rp must be reduced. In order to reduce Rch(on), it is necessary to find new methods to fabricate the semiconductor films which form the thin-film semiconductor device. More specifically, the carrier mobility of the semiconductor films must be increased and the channel portion 402 must be shortened.
The resistances Rs and Rd may be reduced by either increasing the impurity concentration of the source portion and the drain portion or improving the quality of the semiconductor films forming the source and drain portions. To reduce Rc1 and Rc2, barrier metal can be placed at the contact portions 412 and 414. However, it is more effective to simplify the fabrication process by increasing the impurity concentration of the source and drain portions rather than using barrier metal.
The carrier mobility of the semiconductor films are increased by forming the thin-film semiconductor device using polycrystalline silicon (polysilicon). A polycrystalline silicon thin-film semiconductor device generally has carrier mobility of at least approximately 10 cm.sup.2 /V.s, which is far higher than that of an amorphous silicon thin-film semiconductor device.
Three fabrication methods are known in the prior art for fabricating a polycrystalline silicon thin-film semiconductor device of this type, as described below. In the first fabrication method, a polycrystalline silicon film is first deposited by a low-pressure chemical vapor deposition (LPCVD) method at a deposition temperature of approximately 600.degree. C. or more. The size of the regions (islands) of the polycrystalline silicon ranges approximately from 20 nm to 80 nm. The polycrystalline silicon film surface is then thermally oxidized to form the semiconductor layer and gate insulation layer of the thin-film semiconductor device. The boundary surface roughness (center line average height, Ra) between the gate insulation film and gate electrode is at least approximately 3.1 nm. One example of an n-channel type thin-film transistor fabricated by this method has a carrier mobility of approximately 10 cm.sup.2 /V.s to 20 cm.sup.2 /V.s. The average grain area of the semiconductor film is approximately 4,000 to 6,000 nm.sup.2.
In the second fabrication method, an amorphous silicon film is first formed by plasma-enhanced CVD (PECVD). The amorphous silicon film is then annealed in a nitrogen atmosphere at the temperature of 600.degree. C. from about 20 hours to 80 hours. This annealing process converts the amorphous silicon film into a polycrystalline silicon film known as solid-phase crystallization method. The surface of this polycrystalline silicon film is thermally oxidized to form a semiconductor layer and gate insulation layer of the thin-film semiconductor device. After the thin-film semiconductor device is structured, a hydrogen plasma is applied. In this case, an n-channel type thin-film transistor has the carrier mobility of approximately 150 cm.sup.2 /V.s. See S. Takenaka, et al., Jpn. J. Appl. Phys. 29, L2380 (1990).
Page 03
In the third fabrication method, a polycrystalline silicon film is first deposited by LPCVD at a deposition temperature of 610.degree. C. Si.sup.+ is implanted into the polycrystalline silicon film at a dose of approximately 1.5.times.10.sup.15 cm.sup.-2, which converts the polycrystalline silicon film into an amorphous film. The film is then annealed at 600.degree. C. in a nitrogen atmosphere from tens to several hundreds of hours, so that the amorphous silicon is recrystallized into a polycrystalline silicon film. The surface of this polycrystalline silicon film is then thermally oxidized to form a semiconductor layer and gate insulation layer of the thin-film semiconductor device. After the basic structure of the thin-film semiconductor device is completed, a hydrogenated silicon nitride (p-Si N:H) film is deposited by PECVD over the device, and then the device is annealed in a furnace at 400.degree. C. to hydrogenate the device. In this case, an n-channel type thin-film transistor has the carrier mobility of approximately 100 cm.sup.2 /V.s. See T. Noguchi, et al., J. Electrochemical Soc., 134, page 1771 (1987).
The three fabrication methods described above have inherent problems. The second fabrication method provides a thin-film semiconductor device with high carrier mobility, but requires several tens of hours of furnace annealing after the amorphous silicon film is deposited. This process seriously reduces productivity because of the long process time. In addition, a large quantity of particles are generated in the reaction chamber by the PECVD. These particles cause a large number of device defects because they fall on the substrate during the deposition. Therefore, the yield is very poor.
The third fabrication method requires even longer furnace annealing and has a more complicated process than the second fabrication method. If the number of process steps is increased by even one step, the product yield is reduced. The need for several tens of hours to several hundreds of hours of furnace annealing is unrealistic from the mass-production point of view, and is thus not practicable.
The first fabrication method involves the simple method of depositing a polycrystalline silicon film by LPCVD and then forming a thin-film semiconductor device by thermal oxidation. This method is extremely simple and stable and thus well adapted for mass production. However, the first fabrication method produces small average grain area of approximately 4,000 to 6,000 nm.sup.2 and low carrier mobility of 10 cm.sup.2 /V.s to 20 cm.sup.2 /V.s.
The reduction of the contact resistance Rc and the resistances Rs and Rd is described below. TFTs include ordinary TFT structure and a lightly doped drain (LDD) TFT structure. In order to reduce the overall parasitic resistance Rp and the total ON resistance Ron, the LDD-type TFT is preferred.
A method of fabricating ordinary TFTs is described with reference to FIG. 27. In this fabrication method, a gate insulation film 25 is first formed on thin semiconductor films 22 that have been patterned into islands on an insulating substrate 21 and gate electrodes 26 are formed over the semiconductor films 22. Next, donor impurity ions are implanted at high concentration into the thin semiconductor film 22 to form the source and drain regions of the n-channel TFT and form thin n.sup.+ semiconductor films 23. Acceptor impurity ions are implanted at high concentration into the thin semiconductor film 22 which are the source and drain regions of the p-channel TFT and form thin p.sup.+ semiconductor films 24. Since this method implants the impurities by using the gate electrode as a channel mask, the resultant TFT is called a self-aligned TFT. A non-self-aligned TFT is produced by first forming the thin n.sup.+ semiconductor islands and the thin p.sup.+ semiconductor islands that contain appropriate impurities. These TFTs are covered with an interlayer insulation film 27, and then thin metal films 28 are patterned to complete the TFTs.
Page 04
Single-crystal MOSFETs possessing LDD structure are widely used in semiconductor integrated circuits which are made using single-crystal substrates. The LDD MOSFETs restrain the device from generating hot carriers and have high reliability. Conventional fabrication techniques of LDD-type MOSFETs are described in JP 2-58274, JP 2-45972, JP 62-241375 and JP 62-234372.
Since the diffusion coefficient of the impurities in the single-crystal semiconductor material is low, the LDD length can be shortened to approximately one-tenth of the channel length. Therefore, the source-drain current of the transistor on-state (ON-current) of an LDD-type MOSFET is reduced to only about one-tenth of that of an ordinary-structure MOSFET.
In contrast, since TFTs use non-single-crystal thin semiconductor films, the impurity ions have increased diffusion along the grain boundaries of the semiconductor films. The actual diffusion coefficient in poly-Si (polysilicon) films increases by at least one order of magnitude over the diffusion coefficient in the single-crystal semiconductor. Therefore, the LDD length of the LDD-type TFT is long. The longer LDD results in high electric resistance of this LDD portion which cause the ON current to be one-half or less than that of an ordinary TFT structure. For this reason the LDD-type TFT has not been used in circuits that require high speeds.
In the self-aligned ordinary TFTs shown in FIG. 27, impurities are implanted at high concentration into the source and drain portions. Therefore, the parasitic resistance at the source and drain regions is low. However, other problems prevent increasing the speed of the self-aligned ordinary TFTs. The increased diffusion along the grain boundaries increases a parasitic capacitance of the TFT between the gate and the source/drain overlapped regions which results in an increase of MOS capacitance.
As shown in FIG. 27, an overlapping portion of the n-channel TFT indicated by Yjn and an overlapping portion of the p-channel TFT indicated by Yjp form parasitic capacitances. The effective n-channel channel length Leffn and the effective p-channel channel length Leffp are the lengths obtained by subtracting twice the corresponding overlapping portion Yjn or Yjp from the n-channel gate electrode length, Lgaten or the p-channel gate electrode length Lgatep for the p-channel device. These gate electrode lengths are also known as gate electrode widths.
For an effective channel length of 4 .mu.m, a gate electrode length of at least 6 .mu.m is required because these overlapping portions are at least 1 .mu.m long. The increase in the parasitic capacitance of the TFTs is at least a factor of 1.5 compared to the originally desired device. This results in a reduced operating speed of two-thirds or less of the speed of the originally desired TFT. Accordingly, ordinary self-aligned TFTs of the prior art are not used to increase operating speeds.
Page 05
The prior art technique described in JP 5-173179 uses the ordinary TFTs shown in FIG. 27 for the peripheral circuitry because the LDD-type TFTs are not suitable for high-speed operation. LDD-type TFTs are used in the display portion because the liquid crystal of this display portion is a high-resistance material. Thus, it is necessary to restrain the OFF current of the pixel TFTs.
Another prior art using the LDD-type TFTs in the peripheral circuitry and the display portion is described in JP 6-102531. However, even in this prior art, the ON current of each LDD-type TFT is small. The ON current is increased by adding novel processing steps such as solid-phase crystallization and hydrogenation. See page 7, left column, lines 26 to 36 of JP 6-102531.
Although the utilization of the LDD structure has the advantage of preventing leakage currents, additional processing steps must be introduced to compensate for the low ON-current inherent in the LDD structure. JP 6-102531 discloses that the impurity dose implanted into the LDD region is 1.times.10.sup.14 cm.sup.-2 or less. See page 5, left column, lines 45 to 48. This numerical limit is not intended for optimizing the ON/OFF current ratio but for reducing the OFF current and restraining leakage currents.
Therefore, the ON current cannot be increased even though the OFF current can be reduced because, as the impurity dose implanted into the LDD region becomes smaller, the resistance of this LDD region increases and the ON current decreases. Similarly, the impurity dose implanted into the source and drain portions is disclosed to be in the range of between 1.times.10.sup.14 and 1.times.10.sup.17 cm.sup.-2 . See page 5, right column, lines 11 to 14 of JP 6-102531. This numerical limit is neither intended for optimizing the diffusion length due to increased diffusion, nor reducing the resistances Rc, Rs, and Rd.. Furthermore, the channel length is set to 6 .mu.m and no technique is disclosed for reducing the channel length of the TFT to 5 .mu.m or less.
Page 06
As described above, it is difficult to increase the ON current, and to reduce the parasitic resistances Rc, Rs, and Rd while optimizing the diffusion length. Further, it is difficult to reduce channel length. Therefore, it is difficult to apply LDD-type TFTs to high-speed circuits without additional processing steps such as solid-phase crystallization.
An objective of the invention is the provision of a thin-film semiconductor device which can be fabricated by a simple, effective process and which also has good characteristics. A method of fabricating such a thin-film semiconductor device and a display device using this thin-film semiconductor device is provided.
Another objective of the invention is to provide an LDD-type thin-film semiconductor device that is capable of operating at high speed without requiring any additional processing steps. The invention also provides a method for fabricating such a thin-film semiconductor device and a display device using this thin-film semiconductor device.
A further objective of the invention is to provide higher speeds for thin-film semiconductor devices, and to provide a thin-film semiconductor device that replaces single-crystal MOSFETS used in the digital and analog circuits thus broadening the field of application for the thin-film semiconductor devices. A method of fabricating this thin-film semiconductor device is also provided.